A standard ECL logic gate with an ECL cutoff driver circuit is illustrated in FIG. 1. The basic ECL gate is a differential gate provided by the ECL gate transistors Q6 and Q7. In this example gate transistor Q6 provides an input transistor element for receiving ECL data input signals of high and low potential at the input ECL DATA IN. Gate transistor Q7 provides a reference transistor element to which a reference voltage signal REF2 is applied at an intermediate reference voltage level between the high and low potential ECL data input signal levels. The emitter terminals of differential gate transistor elements Q6 and Q7 are coupled together at a common emitter node coupling. Current sink I3 is coupled between the common emitter node coupling and the low potential level power rail designated V.sub.EE.
The current sink I3 is typically a current source transistor element with a tail resistor in its emitter current path for generating the sink current or tail current. A bias voltage generator provides the current source voltage applied to the base of the current source transistor element of the current sink I3.
The ECL differential gate transistor elements Q6 and Q7 provide alternative current paths through respective collector path swing voltage resistors R6 and R7 which are in turn coupled to the high potential level power rail. In this example the high potential level power rail V.sub.CC is at ground potential, and is also designated GND. Typically the swing voltage resistor elements R6 and R7 have substantially equal resistance. Current sink I3 generates the ECL differential gate current in one of the alternative current paths through either of the swing resistors R6 or R7 according to the input signal ECL DATA IN at the base of input transistor element Q6.
Typical ECL gates may also be constructed according to the differential signal input configuration with differential base input circuits. In the differential signal input ECL gate circuit configuration, the differential gate transistors Q6 and Q7 constitute differential input transistors for complementary inputs IN and DN rather than functioning as an input transistor element and reference transistor element as illustrated. Either type of gate is referred to herein as an ECL differential gate, ECL logic gate, or ECL output gate, or simply a differential gate or ECL gate.
As further shown in FIG. 1 the ECL gate output signals are taken from the collector node of gate transistor Q6. The collector node is an output switching node which provides output signals of high and low potential through output buffer emitter follower transistor element Q11 to the output ECL DATA OUT. While the collector node of gate transistor Q6 provides the complemented or inverted output signal for an input signal at ECL DATA IN, a true or non-inverted output signal, not shown, may also be taken from the collector node of gate transistor Q7.
The conventional output cutoff driver circuit for the ECL differential gate is provided by an output enable (OE) differential gate referred to herein as the OE cutoff driver gate. The OE cutoff driver gate includes OE gate transistor elements Q5 and Q8 in which transistor element Q5 provides the OE signal input transistor element or cutoff driver transistor element, and transistor element Q8 provides the OE reference transistor element. The OE gate transistor elements Q5 and Q8 are coupled together at a common emitter node coupling, and current sink I4 is coupled between the common emitter node coupling of OE gate transistor elements Q5 and Q8 and the low potential power rail V.sub.EE. OE signal input transistor element or cutoff driver transistor element Q5 is a multiemitter transistor element or a pair of parallel coupled cutoff driver transistor elements Q5A and Q5B as shown in FIG. 1, with emitter nodes coupled respectively to current sinks I4 and I3 for supplying both current sinks during the cutoff state as hereafter described.
During normal switching operation of the ECL output gate and the output switching node of ECL gate transistor element Q6, the OE signal applied at the base of cutoff transistor elements Q5A and Q5B is low and OE cutoff driver transistor elements Q5A and Q5B are off. The OE reference transistor element Q8 therefore carries the tail current for current sink I4. For the cutoff state, the OE signal applied at the base of cutoff transistor elements Q5A and Q5B is high and OE cutoff driver transistor elements Q5A and Q5B turn on. With transistor elements Q5A and Q5B conducting, the emitter currents satisfy both the current sinks I3 and I4, turning off transistor elements Q7 and Q8. The total sinking current through both current sinks I3 and I4 is forced through load resistor element R6. The abnormally large current causes a large voltage drop across resistor element R6. As a result, the voltage level at the collector node of ECL gate input transistor Q6 and the output ECL DATA OUT drops below the cutoff potential level, approaching a load termination voltage V.sub.TT of, e.g. -2v. The ECL gate output ECL DATA OUT is therefore held in the cutoff or high impedance state for applications with multiple ECL output gates on a common bus. In common bus applications, one ECL output gate may be in the active switching mode while the others are held in the cutoff or high impedance state.
One disadvantage of the conventional ECL gate OE cutoff driver circuit is the large power dissipation required in both the cutoff state and when the cutoff driver circuit is idling or standing by. Power dissipation increases as the number of ECL output gates or ECL logic gates controlled by the OE cutoff driver circuit increases, forcing an increasing number of large currents through load resistors. A high power OE driver or OE signal source is also required to drive multiple bit circuits for multi-bit ECL output gates such as hex-buffers or octal buffers.
As shown in FIG. 1 the OE driver circuit, also referred to herein as the OE signal circuit includes an OE input gate provided by OE input transistor element Q1 to which OE input signals of high and low potential are applied, and the OE reference transistor element Q2 to which a reference signal REF1 of intermediate potential is applied. The OE input gate transistor elements Q1 and Q2 are coupled in a differential gate with a common emitter node. An OE input gate current sink Il is coupled between this common emitter node and the low potential power rail V.sub.EE. The OE input gate transistor elements Q1 and Q2 provide alternative collector resistor current paths through either of the collector resistors R1 and R2 and the common resistor element R3 from the high potential power rail V.sub.CC according to the OE signals applied at the base of the OE input transistor element Q1.
In this example the OE output signal from the OE input gate is taken from the collector node of OE reference transistor element Q2 which provides a switching output node coupled to the emitter follower output buffer transistor element Q3. The emitter follower output buffer transistor element Q3 is coupled through base collector shorted (BCS) transistor element diode Q4 to the base nodes of the OE cutoff driver transistor elements Q5A and Q5B. The output buffer emitter follower transistor element Q3 and the base node of the cutoff driver transistor elements Q5A and Q5B are referenced to the low potential power rail V.sub.EE through current sink I2.
The currents required for operation of the OE driver circuit or OE signal circuit provided by current sinks Il and I2 are relatively small. Each of the current sinks Il and I2 operate at a current level of approximately 1 mA. The OE driver circuit or OE signal circuit may be used for driving multiple ECL logic gates with cutoff driver circuits. As stated above for multiple bit circuits such as hex buffers and octal buffers a higher power OE driver circuit may be required.
The power required for operation of the ECL logic gate and cutoff driver circuit is substantially greater. The current sinks I3 and I4 typically generate for example sinking currents of 4 mA. With both the current sinks I3 and I4 operating at all times, a total sinking current I.sub.EE in addition to other circuit current requirements is flowing at all times. For an ECL octal buffer line driver a total idling current I.sub.EE in excess of 64 mA may be required. As the number of output gates increases, the magnitude of this idling current and accompanying power dissipation may be the limiting factor in circuit size and number of gates.
The prior art cutoff driver circuit is summarized in the simplified block diagram of FIG. 1A showing the functional circuit blocks of the cutoff driver circuit of FIG. 1 with most of the components deleted. The OE cutoff driver gate is coupled to receive output enable (OE) signals of high and low potential. The OE cutoff driver gate is also operatively coupled to the ECL logic gate for holding the ECL logic gate in the cutoff state in response to one of the high and low OE signals. The OE signal circuit or OE driver circuit for providing OE signals of high and low potential to the OE cutoff driver gate includes the OE input gate and the OE emitter follower output buffer which delivers the OE signals to the OE cutoff driver gate. The functional ECL circuit blocks are provided with respective current sinks including the OE cutoff driver current sink I4 for sinking current from the OE cutoff driver gate.